Semiconductor devices may include a plurality of layers stacked one on another. Such semiconductor devices may be fabricated through a sequence of unit processes.
In general, a combination of a photo-lithography process and an etching process may be used to form a hole penetrating a predetermined layer or to form a trench pattern on a predetermined part of the semiconductor device.
As illustrated in example FIG. 1, initially a photo-resist layer may be coated and then photo-resist pattern 20 formed on and/or over the photo-resist layer to have openings 20a at desired positions and have a desired shape through a photo-lithograph process that exposes and develops the photo-resist layer. Continuously, a dry etching process may be performed to vertically form pattern 12 by removing non-etching layer 10 that is exposed through openings 20a of photo-resist pattern 20. Photo-resist pattern 20 may be used as a barrier for etching. A reactive ion etching (RIE) process or an anisotropic etching may be performed as the dry etching process. Photo-resist pattern 20 may then be removed.
As semiconductor devices have become highly integrated, pattern 12 has also become smaller. In order to form such a fine pattern 12, a narrow band of light such as ArF and KrF may be used as a light source for exposing, and corresponding predetermined photo-resist layers that may be optically reacted with the described light sources may be used. However, it is difficult to form fine patterns of several nanometers due to limitations of optical resolution and a photoresist layer.
It is required to develop a method for forming a fine pattern 12 having a line width narrower than about ½ of a minimum line width that may be formed through a typical photo lithography process.
Since photo-resist layer pattern 20 may be used as an etching barrier, photo-resist pattern 20 must be thick enough to endure etching in order to form deep pattern 12. Therefore, it is difficult to secure a margin of a photoresist layer.